AT91SAM9G15-CU

The AT91SAM9G15-CU is a SMART 400MHz 32-bit Embedded Microprocessor unit based on ARM926EJ-S processor. This MPU integrates a rich set of peripherals to support embedded industrial applications that require advanced user interfaces and high-speed communication. The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration and a 10-bit ADC that supports 4-wire/5-wire resistive touchscreen panels. Multiple communication interfaces include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS USB Host and Device and FS USB Host with dedicated on-chip transceivers, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I²S and TWIs. The 10-layer bus matrix coupled with multiple DMA channels ensures uninterrupted data transfers with minimal processor overhead. The external bus interface incorporates controllers for 4-bank and 8-bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories.

• ARM926EJ-S ARM Thumb processor running at up to 400MHz at 1.0V ± 10%
• 16kB Data cache, 16kB Instruction cache, memory management unit
• System running at up to 133MHz
• Power-on reset cells, reset controller, shutdown controller, periodic interval timer, WDT and RTC
• Internal low power 32kHz RC and fast 12MHz RC oscillators
• Selectable 32768Hz low-power oscillator and 12MHz oscillator
• One PLL for the system and one PLL at 480MHz optimized for USB high speed
• Twelve 32-bit-layer AHB bus matrix for large bandwidth transfers
• Dual peripheral bridge with dedicated programmable clock for best performances
• Two dual port 8-channel DMA controllers (DMAC)
• Advanced interrupt controller (AIC) and debug unit (DBGU)
• Two programmable external clock signals
• Shutdown controller with four 32-bit battery backup registers
• Clock generator and power management controller
• Very slow clock operating mode, software programmable power optimization capabilities
• Four 32-bit parallel I/O controllers
• 105 Programmable I/O lines multiplexed with up to three peripheral I/Os
• Input change interrupt capability on each I/O line, optional Schmitt trigger input
• Individually programmable open-drain, pull-up and pull-down resistor, synchronous output
• One 64kB internal ROM embedding bootstrap routine
• One 32kB Internal SRAM, single-cycle access at system speed
• High bandwidth multi-port DDR SDR SDRAM controller (DDRSDRC)
• 32-bit External bus interface supporting 4-bank and 8-bank DDR2/LPDDR, SDR/LPSDR, static memories
• MLC/SLC 8-bit NAND controller w/ up to 24-bit programmable multi-bit error correcting code (PMECC)
• Software modem device (SMD)

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