9DB102BGLFT

9DB102BGLFT is a two output differential buffer for PCIe Gen1 & Gen2. This zero-delay buffer supports PCI Express clocking requirements. It is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL band width to maximize performance in systems with or without spread-spectrum clocking.

• 2V - 0.7V current mode differential output pairs (HCSL)
• CLKREQ# pin for outputs 1 and 4/output enable for Express card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
• Spread spectrum compatible/tracks spreading input clock for low EMI
• SMBus Interface/unused outputs can be disabled
• Cycle-to-cycle jitter <lt/> 35ps, output-to-output skew <lt/> 25ps
• Available in 20-pin TSSOP package
• Temperature range from 0 to +70°C