ADF4111BCPZ-RL7

ADF4111 is a RF PLL frequency synthesizer. It can be used to implement local oscillators in the upconversion and down conversion sections of wireless receivers and transmitters. It consist of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an Ndivider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). It is widely used in application such as base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA), wireless handsets (GSM, PCS, DCS, CDMA, WCDMA), wireless LANS, communications test equipment, CATV equipment etc.

• RF input frequency is 0.08GHz to 1.2GHz at (For lower frequencies, ensure SR <gt/> 30V/µs)
• Operating power supply is 2.7V to 5.5V
• Separate charge pump supply (VP) allows extended tuning voltage in 3V systems
• Programmable ant backlash pulse width, operating temperature range is –40°C to +85°C
• Analog and digital lock detect, RF input sensitivity is −15dBm to 0dBm
• Hardware and software power-down mode
• Phase noise (900MHz output) is −87dBc/Hz typ at @ (1kHz offset and 200kHz PFD frequency)
• REFIN input current is ±100µA max
• REFIN input frequency is 5MHz to 104MHz at (For f <lt/> 5MHz, ensure SR <gt/> 100V/µs)
• Package style is 20-lead frame chip scale package [LFCSP-WQ]

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