AD9528BCPZ

AD9528 is a two-stage PLL with an integrated JESD204B/ JESD204C SYSREF clock generator for multiple device synchronization. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high-frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. Application includes high-performance wireless transceivers, LTE and multicarrier GSM base stations, wireless and broadband infrastructure, medical instrumentation, clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B/JESD204C, low jitter, low phase noise clock distribution, ATE and high-performance instrumentation.

• Dedicated 8-bit dividers on each output
• Maximum output frequency is 1000MHz (all outputs, TA -40°C to +85°C)
• Typical output to output skew is 20ps
• Typical duty cycle is 50% (f <lt/> 500MHz, -40°C to +85°C)
• Digital frequency lock detect, SPI- and I²C-compatible serial control port
• PLL1, provides reference input clock clean-up with external VCXO
• Phase detector rate up to 110MHz, redundant reference inputs
• Automatic and manual reference switchover modes, revertive and nonrevertive switching
• 72-lead LFCSP package
• Temperature range from -40°C to +85°C

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ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party