AD9515BCPZ

AD9515 is a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6GHz. The other output operates to 800MHz in LVDS mode and to 250MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. It is used in application such as low jitter, low phase noise clock distribution, clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers, high performance instrumentation, broadband infrastructure, ATE etc.

• Input frequency is 1.6GHz maximum at (VS = 3.3V ± 5%, TA = 25°C)
• LVPECL clock output frequency is 1.6GHz maximum at (VS = 3.3V ± 5%, TA = 25°C)
• Additive output jitter 225fs rms typical
• LVDS clock output frequency is 800MHz maximum at (VS = 3.3V ± 5%, TA = 25°C)
• CMOS clock output frequency is 250MHz maximum at (VS = 3.3V ± 5%, TA = 25°C)
• LVDS output additive time jitter is 300fs rms typical
• CMOS output additive time jitter is 290fs rms typical
• Device configured with 4-level logic pins
• Operating temperature is -40°C to +85°C
• Package style is 32-lead lead frame chip scale (LFCSP-VQ)

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